Commonly-assigned U.S. Pat. No. 7,164,606, which issued on Jan. 16, 2007, to Poplevine et al., discloses an all-PMOS 4-transistor non-volatile memory (NVM) cell that utilizes reverse Fowler-Nordheim tunneling for programming.
Referring to FIG. 1, as disclosed in U.S. Pat. No. 7,164,606, in accordance with the method of programming an NVM array that includes all-PMOS 4-transistor NVM cells 100 having floating gate electrodes that are commonly-connected to a storage node Ps, for each NVM cell in the array that is to be programmed, all of the electrodes of the cell are grounded. An inhibiting voltage Vn is then applied to the bulk-connected source electrode Vr of the cell's read transistor Pr, to the commonly-connected drain, bulk region and source electrodes Ve of the cell's erase transistor Pe, and to the drain electrode Dr of the read transistor Pr. The source electrode Vp and the drain electrode Dp of the cell's programming transistor Pw are grounded. The voltage applied to the bulk region electrode Vnw of the programming transistor Pw is optional; it can be grounded or it can remain at the inhibiting voltage Vn. For all NVM cells in the array that are not selected for programming, the inhibiting voltage Vn is applied to the Vr, Ve and Dr electrodes and is also applied to the Vp, Dp and Vnw electrodes. For cells to be programmed, the control voltage Vc of the cell's control transistor Pc is then swept from 0V to a maximum programming voltage Vcmax in a programming time Tprog. The control voltage Vc is then ramped down from the maximum programming voltage Vcmax to 0V. All electrodes of the cell and the inhibiting voltage Vn are then returned to ground.
As described in detail in the '606 patent, the all-PMOS 4-transistor NVM cell disclosed therein relies on reverse Fowler-Nordheim tunneling for programming. That is, when the potential difference between the floating gate electrode of the programming transistor of the all-PMOS NVM cell and the drain, source and bulk region electrodes of the programming transistor exceeds a tunneling threshold voltage, electrons tunnel from the drain and source electrodes to the floating gate, making the floating gate negatively charged.
U.S. Pat. No. 7,164,606 is hereby incorporated by reference herein in its entirety to provide background information regarding the present invention.
The all-PMOS 4-transistor NVM cell programming technique disclosed in the '606 patent provides advantages of both low current consumption, allowing the ability to simultaneously program a large number of cells in a cell array without the need for high current power sources, and a simple program sequence. However, the 4-transistor PMOS NVM cell cannot be used in certain integrated circuit fabrication processes wherein n-epitaxial silicon is grown that shorts all N-wells together or where each N-well needs to be surrounded by an individual N+, P+, or trench guard ring and charge will be lost if the floating polysilicon gate crosses the guard ring.
Thus, there is a need for an NVM cell design that can be used in processes where an all-PMOS 4-transistor NVM cell is not possible, but retains the advantages of the all-PMOS 4-transistor cell.